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258
driver/SX1278.c
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@ -9,10 +9,7 @@
#include "SX1278.h" #include "SX1278.h"
#include <string.h> #include <string.h>
SoftSPI_TypeDef *sx1278_spix; uint8_t SX1278_SPIRead(SX1278_t *module, uint8_t addr) {
uint8_t SX1278_SPIRead(SX1278_t *module, uint8_t addr)
{
uint8_t tmp; uint8_t tmp;
SX1278_hw_SPICommand(module->hw, addr); SX1278_hw_SPICommand(module->hw, addr);
tmp = SX1278_hw_SPIReadByte(module->hw); tmp = SX1278_hw_SPIReadByte(module->hw);
@ -20,8 +17,7 @@ uint8_t SX1278_SPIRead(SX1278_t *module, uint8_t addr)
return tmp; return tmp;
} }
void SX1278_SPIWrite(SX1278_t *module, uint8_t addr, uint8_t cmd) void SX1278_SPIWrite(SX1278_t *module, uint8_t addr, uint8_t cmd) {
{
SX1278_hw_SetNSS(module->hw, 0); SX1278_hw_SetNSS(module->hw, 0);
SX1278_hw_SPICommand(module->hw, addr | 0x80); SX1278_hw_SPICommand(module->hw, addr | 0x80);
SX1278_hw_SPICommand(module->hw, cmd); SX1278_hw_SPICommand(module->hw, cmd);
@ -29,20 +25,14 @@ void SX1278_SPIWrite(SX1278_t *module, uint8_t addr, uint8_t cmd)
} }
void SX1278_SPIBurstRead(SX1278_t *module, uint8_t addr, uint8_t *rxBuf, void SX1278_SPIBurstRead(SX1278_t *module, uint8_t addr, uint8_t *rxBuf,
uint8_t length) uint8_t length) {
{
uint8_t i; uint8_t i;
// if (length <= 1) if (length <= 1) {
if (length < 1)
{
return; return;
} } else {
else
{
SX1278_hw_SetNSS(module->hw, 0); SX1278_hw_SetNSS(module->hw, 0);
SX1278_hw_SPICommand(module->hw, addr); SX1278_hw_SPICommand(module->hw, addr);
for (i = 0; i < length; i++) for (i = 0; i < length; i++) {
{
*(rxBuf + i) = SX1278_hw_SPIReadByte(module->hw); *(rxBuf + i) = SX1278_hw_SPIReadByte(module->hw);
} }
SX1278_hw_SetNSS(module->hw, 1); SX1278_hw_SetNSS(module->hw, 1);
@ -50,134 +40,121 @@ void SX1278_SPIBurstRead(SX1278_t *module, uint8_t addr, uint8_t *rxBuf,
} }
void SX1278_SPIBurstWrite(SX1278_t *module, uint8_t addr, uint8_t *txBuf, void SX1278_SPIBurstWrite(SX1278_t *module, uint8_t addr, uint8_t *txBuf,
uint8_t length) uint8_t length) {
{
unsigned char i; unsigned char i;
if (length <= 1) if (length <= 1) {
{
return; return;
} } else {
else
{
SX1278_hw_SetNSS(module->hw, 0); SX1278_hw_SetNSS(module->hw, 0);
SX1278_hw_SPICommand(module->hw, addr | 0x80); SX1278_hw_SPICommand(module->hw, addr | 0x80);
for (i = 0; i < length; i++) for (i = 0; i < length; i++) {
{
SX1278_hw_SPICommand(module->hw, *(txBuf + i)); SX1278_hw_SPICommand(module->hw, *(txBuf + i));
} }
SX1278_hw_SetNSS(module->hw, 1); SX1278_hw_SetNSS(module->hw, 1);
} }
} }
void SX1278_config(SX1278_t *module) void SX1278_config(SX1278_t *module) {
{ SX1278_sleep(module); //Change modem mode Must in Sleep mode
SX1278_sleep(module); // Change modem mode Must in Sleep mode
SX1278_hw_DelayMs(15); SX1278_hw_DelayMs(15);
SX1278_entryLoRa(module); SX1278_entryLoRa(module);
// SX1278_SPIWrite(module, 0x5904); //?? Change digital regulator form 1.6V to 1.47V: see errata note //SX1278_SPIWrite(module, 0x5904); //?? Change digital regulator form 1.6V to 1.47V: see errata note
uint64_t freq = ((uint64_t)module->frequency << 19) / 32000000; uint64_t freq = ((uint64_t) module->frequency << 19) / 32000000;
uint8_t freq_reg[3]; uint8_t freq_reg[3];
freq_reg[0] = (uint8_t)(freq >> 16); freq_reg[0] = (uint8_t) (freq >> 16);
freq_reg[1] = (uint8_t)(freq >> 8); freq_reg[1] = (uint8_t) (freq >> 8);
freq_reg[2] = (uint8_t)(freq >> 0); freq_reg[2] = (uint8_t) (freq >> 0);
SX1278_SPIBurstWrite(module, LR_RegFrMsb, (uint8_t *)freq_reg, 3); // setting frequency parameter SX1278_SPIBurstWrite(module, LR_RegFrMsb, (uint8_t*) freq_reg, 3); //setting frequency parameter
SX1278_SPIWrite(module, RegSyncWord, 0x34); SX1278_SPIWrite(module, RegSyncWord, 0x34);
// setting base parameter //setting base parameter
SX1278_SPIWrite(module, LR_RegPaConfig, SX1278_Power[module->power]); // Setting output power parameter SX1278_SPIWrite(module, LR_RegPaConfig, SX1278_Power[module->power]); //Setting output power parameter
SX1278_SPIWrite(module, LR_RegOcp, 0x0B); // RegOcp,Close Ocp SX1278_SPIWrite(module, LR_RegOcp, 0x0B); //RegOcp,Close Ocp
SX1278_SPIWrite(module, LR_RegLna, 0x23); // RegLNA,High & LNA Enable SX1278_SPIWrite(module, LR_RegLna, 0x23); //RegLNA,High & LNA Enable
if (SX1278_SpreadFactor[module->LoRa_SF] == 6) if (SX1278_SpreadFactor[module->LoRa_SF] == 6) { //SFactor=6
{ // SFactor=6
uint8_t tmp; uint8_t tmp;
SX1278_SPIWrite(module, SX1278_SPIWrite(module,
LR_RegModemConfig1, LR_RegModemConfig1,
((SX1278_LoRaBandwidth[module->LoRa_BW] << 4) + (SX1278_CodingRate[module->LoRa_CR] << 1) + 0x01)); // Implicit Enable CRC Enable(0x02) & Error Coding rate 4/5(0x01), 4/6(0x02), 4/7(0x03), 4/8(0x04) ((SX1278_LoRaBandwidth[module->LoRa_BW] << 4)
+ (SX1278_CodingRate[module->LoRa_CR] << 1) + 0x01)); //Implicit Enable CRC Enable(0x02) & Error Coding rate 4/5(0x01), 4/6(0x02), 4/7(0x03), 4/8(0x04)
SX1278_SPIWrite(module, SX1278_SPIWrite(module,
LR_RegModemConfig2, LR_RegModemConfig2,
((SX1278_SpreadFactor[module->LoRa_SF] << 4) + (SX1278_CRC_Sum[module->LoRa_CRC_sum] << 2) + 0x03)); ((SX1278_SpreadFactor[module->LoRa_SF] << 4)
+ (SX1278_CRC_Sum[module->LoRa_CRC_sum] << 2) + 0x03));
tmp = SX1278_SPIRead(module, 0x31); tmp = SX1278_SPIRead(module, 0x31);
tmp &= 0xF8; tmp &= 0xF8;
tmp |= 0x05; tmp |= 0x05;
SX1278_SPIWrite(module, 0x31, tmp); SX1278_SPIWrite(module, 0x31, tmp);
SX1278_SPIWrite(module, 0x37, 0x0C); SX1278_SPIWrite(module, 0x37, 0x0C);
} } else {
else
{
SX1278_SPIWrite(module, SX1278_SPIWrite(module,
LR_RegModemConfig1, LR_RegModemConfig1,
((SX1278_LoRaBandwidth[module->LoRa_BW] << 4) + (SX1278_CodingRate[module->LoRa_CR] << 1) + 0x00)); // Explicit Enable CRC Enable(0x02) & Error Coding rate 4/5(0x01), 4/6(0x02), 4/7(0x03), 4/8(0x04) ((SX1278_LoRaBandwidth[module->LoRa_BW] << 4)
+ (SX1278_CodingRate[module->LoRa_CR] << 1) + 0x00)); //Explicit Enable CRC Enable(0x02) & Error Coding rate 4/5(0x01), 4/6(0x02), 4/7(0x03), 4/8(0x04)
SX1278_SPIWrite(module, SX1278_SPIWrite(module,
LR_RegModemConfig2, LR_RegModemConfig2,
((SX1278_SpreadFactor[module->LoRa_SF] << 4) + (SX1278_CRC_Sum[module->LoRa_CRC_sum] << 2) + 0x00)); // SFactor & LNA gain set by the internal AGC loop ((SX1278_SpreadFactor[module->LoRa_SF] << 4)
+ (SX1278_CRC_Sum[module->LoRa_CRC_sum] << 2) + 0x00)); //SFactor & LNA gain set by the internal AGC loop
} }
SX1278_SPIWrite(module, LR_RegModemConfig3, 0x04); SX1278_SPIWrite(module, LR_RegModemConfig3, 0x04);
SX1278_SPIWrite(module, LR_RegSymbTimeoutLsb, 0x08); // RegSymbTimeoutLsb Timeout = 0x3FF(Max) SX1278_SPIWrite(module, LR_RegSymbTimeoutLsb, 0x08); //RegSymbTimeoutLsb Timeout = 0x3FF(Max)
SX1278_SPIWrite(module, LR_RegPreambleMsb, 0x00); // RegPreambleMsb SX1278_SPIWrite(module, LR_RegPreambleMsb, 0x00); //RegPreambleMsb
SX1278_SPIWrite(module, LR_RegPreambleLsb, 8); // RegPreambleLsb 8+4=12byte Preamble SX1278_SPIWrite(module, LR_RegPreambleLsb, 8); //RegPreambleLsb 8+4=12byte Preamble
SX1278_SPIWrite(module, REG_LR_DIOMAPPING2, 0x01); // RegDioMapping2 DIO5=00, DIO4=01 SX1278_SPIWrite(module, REG_LR_DIOMAPPING2, 0x01); //RegDioMapping2 DIO5=00, DIO4=01
module->readBytes = 0; module->readBytes = 0;
SX1278_standby(module); // Entry standby mode SX1278_standby(module); //Entry standby mode
} }
void SX1278_standby(SX1278_t *module) void SX1278_standby(SX1278_t *module) {
{
SX1278_SPIWrite(module, LR_RegOpMode, 0x09); SX1278_SPIWrite(module, LR_RegOpMode, 0x09);
module->status = STANDBY; module->status = STANDBY;
} }
void SX1278_sleep(SX1278_t *module) void SX1278_sleep(SX1278_t *module) {
{
SX1278_SPIWrite(module, LR_RegOpMode, 0x08); SX1278_SPIWrite(module, LR_RegOpMode, 0x08);
module->status = SLEEP; module->status = SLEEP;
} }
void SX1278_entryLoRa(SX1278_t *module) void SX1278_entryLoRa(SX1278_t *module) {
{
SX1278_SPIWrite(module, LR_RegOpMode, 0x88); SX1278_SPIWrite(module, LR_RegOpMode, 0x88);
} }
void SX1278_clearLoRaIrq(SX1278_t *module) void SX1278_clearLoRaIrq(SX1278_t *module) {
{
SX1278_SPIWrite(module, LR_RegIrqFlags, 0xFF); SX1278_SPIWrite(module, LR_RegIrqFlags, 0xFF);
} }
int SX1278_LoRaEntryRx(SX1278_t *module, uint8_t length, uint32_t timeout) int SX1278_LoRaEntryRx(SX1278_t *module, uint8_t length, uint32_t timeout) {
{
uint8_t addr; uint8_t addr;
module->packetLength = length; module->packetLength = length;
SX1278_config(module); // Setting base parameter SX1278_config(module); //Setting base parameter
SX1278_SPIWrite(module, REG_LR_PADAC, 0x84); // Normal and RX SX1278_SPIWrite(module, REG_LR_PADAC, 0x84); //Normal and RX
SX1278_SPIWrite(module, LR_RegHopPeriod, 0xFF); // No FHSS SX1278_SPIWrite(module, LR_RegHopPeriod, 0xFF); //No FHSS
SX1278_SPIWrite(module, REG_LR_DIOMAPPING1, 0x01); // DIO=00,DIO1=00,DIO2=00, DIO3=01 SX1278_SPIWrite(module, REG_LR_DIOMAPPING1, 0x01);//DIO=00,DIO1=00,DIO2=00, DIO3=01
SX1278_SPIWrite(module, LR_RegIrqFlagsMask, 0x3F); // Open RxDone interrupt & Timeout SX1278_SPIWrite(module, LR_RegIrqFlagsMask, 0x3F);//Open RxDone interrupt & Timeout
SX1278_clearLoRaIrq(module); SX1278_clearLoRaIrq(module);
SX1278_SPIWrite(module, LR_RegPayloadLength, length); // Payload Length 21byte(this register must difine when the data long of one byte in SF is 6) SX1278_SPIWrite(module, LR_RegPayloadLength, length);//Payload Length 21byte(this register must difine when the data long of one byte in SF is 6)
addr = SX1278_SPIRead(module, LR_RegFifoRxBaseAddr); // Read RxBaseAddr addr = SX1278_SPIRead(module, LR_RegFifoRxBaseAddr); //Read RxBaseAddr
SX1278_SPIWrite(module, LR_RegFifoAddrPtr, addr); // RxBaseAddr->FiFoAddrPtr SX1278_SPIWrite(module, LR_RegFifoAddrPtr, addr); //RxBaseAddr->FiFoAddrPtr
SX1278_SPIWrite(module, LR_RegOpMode, 0x8d); // Mode//Low Frequency Mode SX1278_SPIWrite(module, LR_RegOpMode, 0x8d); //Mode//Low Frequency Mode
// SX1278_SPIWrite(module, LR_RegOpMode,0x05); //Continuous Rx Mode //High Frequency Mode //SX1278_SPIWrite(module, LR_RegOpMode,0x05); //Continuous Rx Mode //High Frequency Mode
module->readBytes = 0; module->readBytes = 0;
while (1) while (1) {
{ if ((SX1278_SPIRead(module, LR_RegModemStat) & 0x04) == 0x04) { //Rx-on going RegModemStat
if ((SX1278_SPIRead(module, LR_RegModemStat) & 0x04) == 0x04)
{ // Rx-on going RegModemStat
module->status = RX; module->status = RX;
return 1; return 1;
} }
if (--timeout == 0) if (--timeout == 0) {
{
SX1278_hw_Reset(module->hw); SX1278_hw_Reset(module->hw);
SX1278_config(module); SX1278_config(module);
return 0; return 0;
@ -186,36 +163,21 @@ int SX1278_LoRaEntryRx(SX1278_t *module, uint8_t length, uint32_t timeout)
} }
} }
uint8_t SX1278_LoRaRxPacket(SX1278_t *module) uint8_t SX1278_LoRaRxPacket(SX1278_t *module) {
{
unsigned char addr; unsigned char addr;
unsigned char packet_size; unsigned char packet_size;
static unsigned char last_addr = 0xff;
// if (SX1278_hw_GetDIO0(module->hw))
{
if (module->LoRa_SF == SX1278_LORA_SF_6)
{ // When SpreadFactor is six,will used Implicit Header mode(Excluding internal packet length)
packet_size = module->packetLength;
}
else
{
packet_size = SX1278_SPIRead(module, LR_RegRxNbBytes); // Number for received bytes
}
if (packet_size == 0)
return 0;
if (SX1278_hw_GetDIO0(module->hw)) {
memset(module->rxBuffer, 0x00, SX1278_MAX_PACKET); memset(module->rxBuffer, 0x00, SX1278_MAX_PACKET);
addr = SX1278_SPIRead(module, LR_RegFifoRxCurrentaddr); // last packet addr addr = SX1278_SPIRead(module, LR_RegFifoRxCurrentaddr); //last packet addr
SX1278_SPIWrite(module, LR_RegFifoAddrPtr, addr); //RxBaseAddr -> FiFoAddrPtr
// if (addr == last_addr) // Judge if new packet arrived if (module->LoRa_SF == SX1278_LORA_SF_6) { //When SpreadFactor is six,will used Implicit Header mode(Excluding internal packet length)
// return 0; packet_size = module->packetLength;
// else } else {
// last_addr = addr; packet_size = SX1278_SPIRead(module, LR_RegRxNbBytes); //Number for received bytes
}
SX1278_SPIWrite(module, LR_RegFifoAddrPtr, addr); // RxBaseAddr -> FiFoAddrPtr
SX1278_SPIBurstRead(module, 0x00, module->rxBuffer, packet_size); SX1278_SPIBurstRead(module, 0x00, module->rxBuffer, packet_size);
module->readBytes = packet_size; module->readBytes = packet_size;
@ -224,34 +186,30 @@ uint8_t SX1278_LoRaRxPacket(SX1278_t *module)
return module->readBytes; return module->readBytes;
} }
int SX1278_LoRaEntryTx(SX1278_t *module, uint8_t length, uint32_t timeout) int SX1278_LoRaEntryTx(SX1278_t *module, uint8_t length, uint32_t timeout) {
{
uint8_t addr; uint8_t addr;
uint8_t temp; uint8_t temp;
module->packetLength = length; module->packetLength = length;
SX1278_config(module); // setting base parameter SX1278_config(module); //setting base parameter
SX1278_SPIWrite(module, REG_LR_PADAC, 0x87); // Tx for 20dBm SX1278_SPIWrite(module, REG_LR_PADAC, 0x87); //Tx for 20dBm
SX1278_SPIWrite(module, LR_RegHopPeriod, 0x00); // RegHopPeriod NO FHSS SX1278_SPIWrite(module, LR_RegHopPeriod, 0x00); //RegHopPeriod NO FHSS
SX1278_SPIWrite(module, REG_LR_DIOMAPPING1, 0x41); // DIO0=01, DIO1=00,DIO2=00, DIO3=01 SX1278_SPIWrite(module, REG_LR_DIOMAPPING1, 0x41); //DIO0=01, DIO1=00,DIO2=00, DIO3=01
SX1278_clearLoRaIrq(module); SX1278_clearLoRaIrq(module);
SX1278_SPIWrite(module, LR_RegIrqFlagsMask, 0xF7); // Open TxDone interrupt SX1278_SPIWrite(module, LR_RegIrqFlagsMask, 0xF7); //Open TxDone interrupt
SX1278_SPIWrite(module, LR_RegPayloadLength, length); // RegPayloadLength 21byte SX1278_SPIWrite(module, LR_RegPayloadLength, length); //RegPayloadLength 21byte
addr = SX1278_SPIRead(module, LR_RegFifoTxBaseAddr); // RegFiFoTxBaseAddr addr = SX1278_SPIRead(module, LR_RegFifoTxBaseAddr); //RegFiFoTxBaseAddr
SX1278_SPIWrite(module, LR_RegFifoAddrPtr, addr); // RegFifoAddrPtr SX1278_SPIWrite(module, LR_RegFifoAddrPtr, addr); //RegFifoAddrPtr
while (1) while (1) {
{
temp = SX1278_SPIRead(module, LR_RegPayloadLength); temp = SX1278_SPIRead(module, LR_RegPayloadLength);
if (temp == length) if (temp == length) {
{
module->status = TX; module->status = TX;
return 1; return 1;
} }
if (--timeout == 0) if (--timeout == 0) {
{
SX1278_hw_Reset(module->hw); SX1278_hw_Reset(module->hw);
SX1278_config(module); SX1278_config(module);
return 0; return 0;
@ -260,36 +218,29 @@ int SX1278_LoRaEntryTx(SX1278_t *module, uint8_t length, uint32_t timeout)
} }
int SX1278_LoRaTxPacket(SX1278_t *module, uint8_t *txBuffer, uint8_t length, int SX1278_LoRaTxPacket(SX1278_t *module, uint8_t *txBuffer, uint8_t length,
uint32_t timeout) uint32_t timeout) {
{
SX1278_SPIBurstWrite(module, 0x00, txBuffer, length); SX1278_SPIBurstWrite(module, 0x00, txBuffer, length);
SX1278_SPIWrite(module, LR_RegOpMode, 0x8b); // Tx Mode SX1278_SPIWrite(module, LR_RegOpMode, 0x8b); //Tx Mode
while (1) {
{ if (SX1278_hw_GetDIO0(module->hw)) { //if(Get_NIRQ()) //Packet send over
// if (SX1278_hw_GetDIO0(module->hw))
{ // if(Get_NIRQ()) //Packet send over
SX1278_SPIRead(module, LR_RegIrqFlags); SX1278_SPIRead(module, LR_RegIrqFlags);
SX1278_clearLoRaIrq(module); // Clear irq SX1278_clearLoRaIrq(module); //Clear irq
SX1278_standby(module); // Entry Standby mode SX1278_standby(module); //Entry Standby mode
return 1; return 1;
} }
// if (--timeout == 0) if (--timeout == 0) {
// { SX1278_hw_Reset(module->hw);
// SX1278_hw_Reset(module->hw); SX1278_config(module);
// SX1278_config(module); return 0;
// return 0; }
// } SX1278_hw_DelayMs(1);
// SX1278_hw_DelayMs(1);
} }
} }
void SX1278_init(SX1278_t *module, uint64_t frequency, uint8_t power, void SX1278_init(SX1278_t *module, uint64_t frequency, uint8_t power,
uint8_t LoRa_SF, uint8_t LoRa_BW, uint8_t LoRa_CR, uint8_t LoRa_SF, uint8_t LoRa_BW, uint8_t LoRa_CR,
uint8_t LoRa_CRC_sum, uint8_t packetLength) uint8_t LoRa_CRC_sum, uint8_t packetLength) {
{
sx1278_spix = module->hw->spi;
SX1278_hw_init(module->hw); SX1278_hw_init(module->hw);
module->frequency = frequency; module->frequency = frequency;
module->power = power; module->power = power;
@ -302,47 +253,40 @@ void SX1278_init(SX1278_t *module, uint64_t frequency, uint8_t power,
} }
int SX1278_transmit(SX1278_t *module, uint8_t *txBuf, uint8_t length, int SX1278_transmit(SX1278_t *module, uint8_t *txBuf, uint8_t length,
uint32_t timeout) uint32_t timeout) {
{ if (SX1278_LoRaEntryTx(module, length, timeout)) {
if (SX1278_LoRaEntryTx(module, length, timeout))
{
return SX1278_LoRaTxPacket(module, txBuf, length, timeout); return SX1278_LoRaTxPacket(module, txBuf, length, timeout);
} }
return 0; return 0;
} }
int SX1278_receive(SX1278_t *module, uint8_t length, uint32_t timeout) int SX1278_receive(SX1278_t *module, uint8_t length, uint32_t timeout) {
{
return SX1278_LoRaEntryRx(module, length, timeout); return SX1278_LoRaEntryRx(module, length, timeout);
} }
uint8_t SX1278_available(SX1278_t *module) uint8_t SX1278_available(SX1278_t *module) {
{
return SX1278_LoRaRxPacket(module); return SX1278_LoRaRxPacket(module);
} }
uint8_t SX1278_read(SX1278_t *module, uint8_t *rxBuf, uint8_t length) uint8_t SX1278_read(SX1278_t *module, uint8_t *rxBuf, uint8_t length) {
{
if (length != module->readBytes) if (length != module->readBytes)
length = module->readBytes; length = module->readBytes;
memcpy(rxBuf, module->rxBuffer, length); memcpy(rxBuf, module->rxBuffer, length);
// rxBuf[length] = '\0'; rxBuf[length] = '\0';
module->readBytes = 0; module->readBytes = 0;
return length; return length;
} }
uint8_t SX1278_RSSI_LoRa(SX1278_t *module) uint8_t SX1278_RSSI_LoRa(SX1278_t *module) {
{
uint32_t temp = 10; uint32_t temp = 10;
temp = SX1278_SPIRead(module, LR_RegRssiValue); // Read RegRssiValue, Rssi value temp = SX1278_SPIRead(module, LR_RegRssiValue); //Read RegRssiValue, Rssi value
temp = temp + 127 - 137; // 127:Max RSSI, 137:RSSI offset temp = temp + 127 - 137; //127:Max RSSI, 137:RSSI offset
return (uint8_t)temp; return (uint8_t) temp;
} }
uint8_t SX1278_RSSI(SX1278_t *module) uint8_t SX1278_RSSI(SX1278_t *module) {
{
uint8_t temp = 0xff; uint8_t temp = 0xff;
temp = SX1278_SPIRead(module, RegRssiValue); temp = SX1278_SPIRead(module, RegRssiValue);
temp = 127 - (temp >> 1); // 127:Max RSSI temp = 127 - (temp >> 1); //127:Max RSSI
return temp; return temp;
} }

41
driver/SX1278.h
View File

@ -17,7 +17,7 @@
#define SX1278_MAX_PACKET 256 #define SX1278_MAX_PACKET 256
#define SX1278_DEFAULT_TIMEOUT 3000 #define SX1278_DEFAULT_TIMEOUT 3000
// RFM98 Internal registers Address //RFM98 Internal registers Address
/********************LoRa mode***************************/ /********************LoRa mode***************************/
#define LR_RegFifo 0x00 #define LR_RegFifo 0x00
// Common settings // Common settings
@ -152,12 +152,11 @@
#define SX1278_POWER_14DBM 2 #define SX1278_POWER_14DBM 2
#define SX1278_POWER_11DBM 3 #define SX1278_POWER_11DBM 3
static const uint8_t SX1278_Power[4] = { static const uint8_t SX1278_Power[4] = { 0xFF, //20dbm
0xFF, // 20dbm 0xFC, //17dbm
0xFC, // 17dbm 0xF9, //14dbm
0xF9, // 14dbm 0xF6, //11dbm
0xF6, // 11dbm };
};
#define SX1278_LORA_SF_6 0 #define SX1278_LORA_SF_6 0
#define SX1278_LORA_SF_7 1 #define SX1278_LORA_SF_7 1
@ -167,7 +166,7 @@ static const uint8_t SX1278_Power[4] = {
#define SX1278_LORA_SF_11 5 #define SX1278_LORA_SF_11 5
#define SX1278_LORA_SF_12 6 #define SX1278_LORA_SF_12 6
static const uint8_t SX1278_SpreadFactor[7] = {6, 7, 8, 9, 10, 11, 12}; static const uint8_t SX1278_SpreadFactor[7] = { 6, 7, 8, 9, 10, 11, 12 };
#define SX1278_LORA_BW_7_8KHZ 0 #define SX1278_LORA_BW_7_8KHZ 0
#define SX1278_LORA_BW_10_4KHZ 1 #define SX1278_LORA_BW_10_4KHZ 1
@ -180,8 +179,7 @@ static const uint8_t SX1278_SpreadFactor[7] = {6, 7, 8, 9, 10, 11, 12};
#define SX1278_LORA_BW_250KHZ 8 #define SX1278_LORA_BW_250KHZ 8
#define SX1278_LORA_BW_500KHZ 9 #define SX1278_LORA_BW_500KHZ 9
static const uint8_t SX1278_LoRaBandwidth[10] = { static const uint8_t SX1278_LoRaBandwidth[10] = { 0, // 7.8KHz,
0, // 7.8KHz,
1, // 10.4KHz, 1, // 10.4KHz,
2, // 15.6KHz, 2, // 15.6KHz,
3, // 20.8KHz, 3, // 20.8KHz,
@ -191,34 +189,27 @@ static const uint8_t SX1278_LoRaBandwidth[10] = {
7, // 125.0KHz, 7, // 125.0KHz,
8, // 250.0KHz, 8, // 250.0KHz,
9 // 500.0KHz 9 // 500.0KHz
}; };
// Coding rate //Coding rate
#define SX1278_LORA_CR_4_5 0 #define SX1278_LORA_CR_4_5 0
#define SX1278_LORA_CR_4_6 1 #define SX1278_LORA_CR_4_6 1
#define SX1278_LORA_CR_4_7 2 #define SX1278_LORA_CR_4_7 2
#define SX1278_LORA_CR_4_8 3 #define SX1278_LORA_CR_4_8 3
static const uint8_t SX1278_CodingRate[4] = {0x01, 0x02, 0x03, 0x04}; static const uint8_t SX1278_CodingRate[4] = { 0x01, 0x02, 0x03, 0x04 };
// CRC Enable //CRC Enable
#define SX1278_LORA_CRC_EN 0 #define SX1278_LORA_CRC_EN 0
#define SX1278_LORA_CRC_DIS 1 #define SX1278_LORA_CRC_DIS 1
static const uint8_t SX1278_CRC_Sum[2] = {0x01, 0x00}; static const uint8_t SX1278_CRC_Sum[2] = { 0x01, 0x00 };
typedef enum _SX1278_STATUS typedef enum _SX1278_STATUS {
{ SLEEP, STANDBY, TX, RX
SLEEP,
STANDBY,
TX,
RX
} SX1278_Status_t; } SX1278_Status_t;
#define RECEIVE_PACKET_LENGTH 1 typedef struct {
typedef struct
{
SX1278_hw_t *hw; SX1278_hw_t *hw;
uint64_t frequency; uint64_t frequency;

50
driver/SX1278_hw.c
View File

@ -8,28 +8,20 @@
#include "SX1278_hw.h" #include "SX1278_hw.h"
#include <string.h> #include <string.h>
#include "systick.h" #include "gpio.h"
#include "softspi.h" #include "spi.h"
#define SetSS SoftSPI_SetSS(sx1278_spix) __weak void SX1278_hw_init(SX1278_hw_t *hw) {
#define ClrSS SoftSPI_ClrSS(sx1278_spix)
#define SPI_WriteRead(__byte__) SoftSPI_WriteRead(sx1278_spix, __byte__)
extern SoftSPI_TypeDef *sx1278_spix;
void SX1278_hw_init(SX1278_hw_t *hw)
{
SX1278_hw_SetNSS(hw, 1); SX1278_hw_SetNSS(hw, 1);
HAL_GPIO_WritePin(hw->reset.port, hw->reset.pin, GPIO_PIN_SET); HAL_GPIO_WritePin(hw->reset.port, hw->reset.pin, GPIO_PIN_SET);
} }
void SX1278_hw_SetNSS(SX1278_hw_t *hw, int value) __weak void SX1278_hw_SetNSS(SX1278_hw_t *hw, int value) {
{ HAL_GPIO_WritePin(hw->nss.port, hw->nss.pin,
(value == 1) ? SetSS : ClrSS; (value == 1) ? GPIO_PIN_SET : GPIO_PIN_RESET);
} }
void SX1278_hw_Reset(SX1278_hw_t *hw) __weak void SX1278_hw_Reset(SX1278_hw_t *hw) {
{
SX1278_hw_SetNSS(hw, 1); SX1278_hw_SetNSS(hw, 1);
HAL_GPIO_WritePin(hw->reset.port, hw->reset.pin, GPIO_PIN_RESET); HAL_GPIO_WritePin(hw->reset.port, hw->reset.pin, GPIO_PIN_RESET);
@ -40,29 +32,29 @@ void SX1278_hw_Reset(SX1278_hw_t *hw)
SX1278_hw_DelayMs(100); SX1278_hw_DelayMs(100);
} }
void SX1278_hw_SPICommand(SX1278_hw_t *hw, uint8_t cmd) __weak void SX1278_hw_SPICommand(SX1278_hw_t *hw, uint8_t cmd) {
{
SX1278_hw_SetNSS(hw, 0); SX1278_hw_SetNSS(hw, 0);
SPI_WriteRead(cmd); HAL_SPI_Transmit(hw->spi, &cmd, 1, 1000);
while (HAL_SPI_GetState(hw->spi) != HAL_SPI_STATE_READY)
;
} }
uint8_t SX1278_hw_SPIReadByte(SX1278_hw_t *hw) __weak uint8_t SX1278_hw_SPIReadByte(SX1278_hw_t *hw) {
{
uint8_t txByte = 0x00; uint8_t txByte = 0x00;
uint8_t rxByte = 0x00; uint8_t rxByte = 0x00;
SX1278_hw_SetNSS(hw, 0); SX1278_hw_SetNSS(hw, 0);
rxByte = SPI_WriteRead(txByte); HAL_SPI_TransmitReceive(hw->spi, &txByte, &rxByte, 1, 1000);
while (HAL_SPI_GetState(hw->spi) != HAL_SPI_STATE_READY)
;
return rxByte; return rxByte;
} }
void SX1278_hw_DelayMs(uint32_t msec) __weak void SX1278_hw_DelayMs(uint32_t msec) {
{ HAL_Delay(msec);
Delay_ms(msec); }
__weak int SX1278_hw_GetDIO0(SX1278_hw_t *hw) {
return (HAL_GPIO_ReadPin(hw->dio0.port, hw->dio0.pin) == GPIO_PIN_SET);
} }
// int SX1278_hw_GetDIO0(SX1278_hw_t *hw)
// {
// return (HAL_GPIO_ReadPin(hw->dio0.port, hw->dio0.pin) == GPIO_PIN_SET);
// }

12
driver/SX1278_hw.h
View File

@ -9,20 +9,17 @@
#define __SX1278_HW_HEADER #define __SX1278_HW_HEADER
#include <stdint.h> #include <stdint.h>
#include "softspi.h"
typedef struct typedef struct {
{
int pin; int pin;
void *port; void *port;
} SX1278_hw_dio_t; } SX1278_hw_dio_t;
typedef struct typedef struct {
{
SX1278_hw_dio_t reset; SX1278_hw_dio_t reset;
SX1278_hw_dio_t dio0; SX1278_hw_dio_t dio0;
SX1278_hw_dio_t nss; SX1278_hw_dio_t nss;
SoftSPI_TypeDef *spi; void *spi;
} SX1278_hw_t; } SX1278_hw_t;
/** /**
@ -92,6 +89,7 @@ void SX1278_hw_DelayMs(uint32_t msec);
* *
* \return 0 if DIO0 low, 1 if DIO high * \return 0 if DIO0 low, 1 if DIO high
*/ */
// int SX1278_hw_GetDIO0(SX1278_hw_t *hw); int SX1278_hw_GetDIO0(SX1278_hw_t *hw);
#endif #endif