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STM32-Player-Doc/STM32H743VI 开发版/STM32H750驱动例程(HAL库)/例33 USB读卡器(Slave)/SYSTEM/sys/sys.c

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新增开发版例程
2021-07-28 13:15:22 +08:00
#include "sys.h"
//////////////////////////////////////////////////////////////////////////////////
/*************************************************************************/
//ϵͳʱ<CDB3>ӳ<EFBFBD>ʼ<EFBFBD><CABC>
//STM32H7<48><37><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3>-HAL<41>⺯<EFBFBD><E2BAAF><EFBFBD>汾
//DevEBox <20><>Խ<EFBFBD><D4BD><EFBFBD><EFBFBD>
//<2F>Ա<EFBFBD><D4B1><EFBFBD><EFBFBD>̣<EFBFBD>mcudev.taobao.com
//<2F>Ա<EFBFBD><D4B1><EFBFBD><EFBFBD>̣<EFBFBD>shop389957290.taobao.com
/*************************************************************************/
//////////////////////////////////////////////////////////////////////////////////
//ʹ<><CAB9>CPU<50><55>L1-Cache
void Cache_Enable(void)
{
SCB_EnableICache();//ʹ<><CAB9>I-Cache
SCB_EnableDCache();//ʹ<><CAB9>D-Cache
SCB->CACR|=1<<2; //ǿ<><C7BF>D-Cache͸д,<2C>粻<EFBFBD><E7B2BB><EFBFBD><EFBFBD>,ʵ<><CAB5>ʹ<EFBFBD><CAB9><EFBFBD>п<EFBFBD><D0BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
}
//ʱ<><CAB1><EFBFBD><EFBFBD><EFBFBD>ú<EFBFBD><C3BA><EFBFBD>
//Fvco=Fs*(plln/pllm);
//Fsys=Fvco/pllp=Fs*(plln/(pllm*pllp));
//Fq=Fvco/pllq=Fs*(plln/(pllm*pllq));
//Fvco:VCOƵ<4F><C6B5>
//Fsys:ϵͳʱ<CDB3><CAB1>Ƶ<EFBFBD><C6B5>,Ҳ<><D2B2>PLL1<4C><31>p<EFBFBD><70>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>Ƶ<EFBFBD><C6B5>
//Fq:PLL1<4C><31>q<EFBFBD><71>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>Ƶ<EFBFBD><C6B5>
//Fs:PLL<4C><4C><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>Ƶ<EFBFBD><C6B5>,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>HSI,CSI,HSE<53><45>.
//plln:PLL1<4C><31>Ƶϵ<C6B5><CFB5>(PLL<4C><4C>Ƶ),ȡֵ<C8A1><D6B5>Χ:4~512.
//pllm:PLL1Ԥ<31><D4A4>Ƶϵ<C6B5><CFB5>(<28><>PLL֮ǰ<D6AE>ķ<EFBFBD>Ƶ),ȡֵ<C8A1><D6B5>Χ:2~63.
//pllp:PLL1<4C><31>p<EFBFBD><70>Ƶϵ<C6B5><CFB5>(PLL֮<4C><D6AE><EFBFBD>ķ<EFBFBD>Ƶ),<2C><>Ƶ<EFBFBD><C6B5><EFBFBD><EFBFBD>Ϊϵͳʱ<CDB3><CAB1>,ȡֵ<C8A1><D6B5>Χ:2~128.(<28>ұ<EFBFBD><D2B1><EFBFBD><EFBFBD><EFBFBD>2<EFBFBD>ı<EFBFBD><C4B1><EFBFBD>)
//pllq:PLL1<4C><31>q<EFBFBD><71>Ƶϵ<C6B5><CFB5>(PLL֮<4C><D6AE><EFBFBD>ķ<EFBFBD>Ƶ),ȡֵ<C8A1><D6B5>Χ:1~128.
//CPUƵ<55><C6B5>(rcc_c_ck)=sys_d1cpre_ck=400Mhz
//rcc_aclk=rcc_hclk3=200Mhz
//AHB1/2/3/4(rcc_hclk1/2/3/4)=200Mhz
//APB1/2/3/4(rcc_pclk1/2/3/4)=100Mhz
//FMCʱ<43><CAB1>Ƶ<EFBFBD><C6B5>=pll2_r_ck=((25/25)*512/2)=256Mhz
//<2F>ⲿ<EFBFBD><E2B2BF><EFBFBD><EFBFBD>Ϊ25M<35><4D>ʱ<EFBFBD><CAB1>,<2C>Ƽ<EFBFBD>ֵ:plln=160,pllm=5,pllp=2,pllq=2.
//<2F>õ<EFBFBD>:Fvco=25*(160/5)=800Mhz
// Fsys=800/2=400Mhz
// Fq=800/2=400Mhz
//<2F><><EFBFBD><EFBFBD>ֵ:0,<2C>ɹ<EFBFBD>;1,ʧ<>ܡ<EFBFBD>
void Stm32_Clock_Init(u32 plln,u32 pllm,u32 pllp,u32 pllq)
{
HAL_StatusTypeDef ret=HAL_OK;
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
MODIFY_REG(PWR->CR3,PWR_CR3_SCUEN, 0);
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
while ((PWR->D3CR & (PWR_D3CR_VOSRDY)) != PWR_D3CR_VOSRDY) {}
//ʹ<><CAB9>HSI48MHz<48><7A>USBʹ<42><CAB9>
RCC_OscInitStruct.OscillatorType=RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState=RCC_HSE_ON;
RCC_OscInitStruct.HSI48State=RCC_HSI48_ON;
RCC_OscInitStruct.HSIState=RCC_HSI_OFF;
RCC_OscInitStruct.CSIState=RCC_CSI_OFF;
RCC_OscInitStruct.PLL.PLLState=RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource=RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLN=plln;
RCC_OscInitStruct.PLL.PLLM=pllm;
RCC_OscInitStruct.PLL.PLLP=pllp;
RCC_OscInitStruct.PLL.PLLQ=pllq;
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
RCC_OscInitStruct.PLL.PLLFRACN = 0;
ret=HAL_RCC_OscConfig(&RCC_OscInitStruct);
if(ret!=HAL_OK) while(1);
RCC_ClkInitStruct.ClockType=(RCC_CLOCKTYPE_SYSCLK|\
RCC_CLOCKTYPE_HCLK |\
RCC_CLOCKTYPE_D1PCLK1 |\
RCC_CLOCKTYPE_PCLK1 |\
RCC_CLOCKTYPE_PCLK2 |\
RCC_CLOCKTYPE_D3PCLK1);
RCC_ClkInitStruct.SYSCLKSource= RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.SYSCLKDivider=RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.AHBCLKDivider=RCC_HCLK_DIV2;
RCC_ClkInitStruct.APB1CLKDivider=RCC_APB1_DIV2;
RCC_ClkInitStruct.APB2CLKDivider=RCC_APB2_DIV2;
RCC_ClkInitStruct.APB3CLKDivider=RCC_APB3_DIV2;
RCC_ClkInitStruct.APB4CLKDivider=RCC_APB4_DIV4;
ret=HAL_RCC_ClockConfig(&RCC_ClkInitStruct,FLASH_LATENCY_2);
if(ret!=HAL_OK) while(1);
__HAL_RCC_CSI_ENABLE() ;
__HAL_RCC_SYSCFG_CLK_ENABLE() ;
HAL_EnableCompensationCell();
}
#ifdef USE_FULL_ASSERT
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʾ<EFBFBD><CABE><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1><EFBFBD>˺<EFBFBD><CBBA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><C4BC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
//file<6C><65>ָ<EFBFBD><D6B8>Դ<EFBFBD>ļ<EFBFBD>
//line<6E><65>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD><EFBFBD>ļ<EFBFBD><C4BC>е<EFBFBD><D0B5><EFBFBD><EFBFBD><EFBFBD>
void assert_failed(uint8_t* file, uint32_t line)
{
while (1)
{
}
}
#endif
//<2F>ж<EFBFBD>I_Cache<68>Ƿ<EFBFBD><C7B7><EFBFBD><EFBFBD><EFBFBD>
//<2F><><EFBFBD><EFBFBD>ֵ:0 <20>رգ<D8B1>1 <20><><EFBFBD><EFBFBD>
u8 Get_ICahceSta(void)
{
u8 sta;
sta=((SCB->CCR)>>17)&0X01;
return sta;
}
//<2F>ж<EFBFBD>I_Dache<68>Ƿ<EFBFBD><C7B7><EFBFBD><EFBFBD><EFBFBD>
//<2F><><EFBFBD><EFBFBD>ֵ:0 <20>رգ<D8B1>1 <20><><EFBFBD><EFBFBD>
u8 Get_DCahceSta(void)
{
u8 sta;
sta=((SCB->CCR)>>16)&0X01;
return sta;
}
#if defined(__clang__) //ʹ<><CAB9>V6<56><36><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(clang)
//THUMBָ<42>֧<EEB2BB>ֻ<EFBFBD><D6BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>·<EFBFBD><C2B7><EFBFBD>ʵ<EFBFBD><CAB5>ִ<EFBFBD>л<EFBFBD><D0BB><EFBFBD>ָ<EFBFBD><D6B8>WFI
void __attribute__((noinline)) WFI_SET(void)
{
__asm__("wfi");
}
//<2F>ر<EFBFBD><D8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>(<28><><EFBFBD>Dz<EFBFBD><C7B2><EFBFBD><EFBFBD><EFBFBD>fault<6C><74>NMI<4D>ж<EFBFBD>)
void __attribute__((noinline)) INTX_DISABLE(void)
{
__asm__("cpsid i \t\n"
"bx lr");
}
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
void __attribute__((noinline)) INTX_ENABLE(void)
{
__asm__("cpsie i \t\n"
"bx lr");
}
//<2F><><EFBFBD><EFBFBD>ջ<EFBFBD><D5BB><EFBFBD><EFBFBD>ַ
//addr:ջ<><D5BB><EFBFBD><EFBFBD>ַ
void __attribute__((noinline)) MSR_MSP(u32 addr)
{
__asm__("msr msp, r0 \t\n"
"bx r14");
}
#elif defined (__CC_ARM) //ʹ<><CAB9>V5<56><35><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(ARMCC)
//THUMBָ<42>֧<EEB2BB>ֻ<EFBFBD><D6BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>·<EFBFBD><C2B7><EFBFBD>ʵ<EFBFBD><CAB5>ִ<EFBFBD>л<EFBFBD><D0BB><EFBFBD>ָ<EFBFBD><D6B8>WFI
__asm void WFI_SET(void)
{
WFI;
}
//<2F>ر<EFBFBD><D8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>(<28><><EFBFBD>Dz<EFBFBD><C7B2><EFBFBD><EFBFBD><EFBFBD>fault<6C><74>NMI<4D>ж<EFBFBD>)
__asm void INTX_DISABLE(void)
{
CPSID I
BX LR
}
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
__asm void INTX_ENABLE(void)
{
CPSIE I
BX LR
}
//<2F><><EFBFBD><EFBFBD>ջ<EFBFBD><D5BB><EFBFBD><EFBFBD>ַ
//addr:ջ<><D5BB><EFBFBD><EFBFBD>ַ
__asm void MSR_MSP(u32 addr)
{
MSR MSP, r0 //set Main Stack value
BX r14
}
#endif
/*************************************************************************/
//ϵͳʱ<CDB3>ӳ<EFBFBD>ʼ<EFBFBD><CABC>
//STM32H7<48><37><EFBFBD><EFBFBD>ģ<EFBFBD><C4A3>-HAL<41>⺯<EFBFBD><E2BAAF><EFBFBD>汾
//DevEBox <20><>Խ<EFBFBD><D4BD><EFBFBD><EFBFBD>
//<2F>Ա<EFBFBD><D4B1><EFBFBD><EFBFBD>̣<EFBFBD>mcudev.taobao.com
//<2F>Ա<EFBFBD><D4B1><EFBFBD><EFBFBD>̣<EFBFBD>shop389957290.taobao.com
/*************************************************************************/
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