2021-08-04 10:46:24 +08:00
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//ϵͳ<CFB5><CDB3>ʼ<EFBFBD><CABC>
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#ifndef __SYS_H
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#define __SYS_H
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#include "stm32h7xx.h"
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#include "core_cm7.h"
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#include "stm32h7xx_hal.h"
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#define Write_Through() (*(__IO uint32_t *)0XE000EF9C = 1UL << 2) //Cache дģʽ
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2021-08-10 15:01:54 +08:00
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void MPU_Config(void);
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2021-08-04 10:46:24 +08:00
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void Cache_Enable(void);
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uint8_t Clock_Init(uint32_t plln, uint32_t pllm, uint32_t pllp, uint32_t pllq);
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uint8_t Get_ICacheSta(void);
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uint8_t Get_DCacheSta(void);
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void QSPI_Enable_Memmapmode(void);
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#if defined(__clang__)
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void __attribute__((noinline)) WFI_SET(void);
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void __attribute__((noinline)) INTX_DISABLE(void);
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void __attribute__((noinline)) INTX_ENABLE(void);
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void __attribute__((noinline)) MSR_MSP(uint32_t addr);
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#elif defined(__CC_ARM)
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void WFI_SET(void);
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void INTX_DISABLE(void);
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void INTX_ENABLE(void);
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void MSR_MSP(uint32_t addr);
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#endif
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#endif
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