STM32-Player/System/sys/sys.c

//ϵͳ<CFB5><CDB3>ʼ<EFBFBD><CABC>

#include "sys.h"

/**
  * @brief  <EFBFBD><EFBFBD><EFBFBD><EFBFBD> MPU
  */
void MPU_Config(void)
{
    MPU_Region_InitTypeDef MPU_InitStruct;

    /* <20><>ֹ MPU */
    HAL_MPU_Disable();

    /* <20><><EFBFBD><EFBFBD>AXI SRAM<41><4D>MPU<50><55><EFBFBD><EFBFBD>ΪWrite through, read allocate<74><65>no write allocate */
    MPU_InitStruct.Enable = MPU_REGION_ENABLE;
    MPU_InitStruct.BaseAddress = 0x24000000;
    MPU_InitStruct.Size = MPU_REGION_SIZE_512KB;
    MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
    MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
    MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
    MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
    MPU_InitStruct.Number = MPU_REGION_NUMBER0;
    MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
    MPU_InitStruct.SubRegionDisable = 0x00;
    MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;

    HAL_MPU_ConfigRegion(&MPU_InitStruct);

    /* <20><><EFBFBD><EFBFBD>FMC<4D><43>չIO<49><4F>MPU<50><55><EFBFBD><EFBFBD>ΪDevice<63><65><EFBFBD><EFBFBD>Strongly Ordered */
    MPU_InitStruct.Enable = MPU_REGION_ENABLE;
    MPU_InitStruct.BaseAddress = 0x60000000;
    MPU_InitStruct.Size = ARM_MPU_REGION_SIZE_64KB;
    MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
    MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
    MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; /* <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>MPU_ACCESS_CACHEABLE;<3B><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>2<EFBFBD><32>CS<43><53>WE<57>ź<EFBFBD> */
    MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
    MPU_InitStruct.Number = MPU_REGION_NUMBER1;
    MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
    MPU_InitStruct.SubRegionDisable = 0x00;
    MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;

    HAL_MPU_ConfigRegion(&MPU_InitStruct);

    /* <20><><EFBFBD><EFBFBD>SRAM4<4D><34><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ΪWrite through, read allocate<74><65>no write allocate */
    MPU_InitStruct.Enable = MPU_REGION_ENABLE;
    MPU_InitStruct.BaseAddress = 0x38000000;
    MPU_InitStruct.Size = ARM_MPU_REGION_SIZE_64KB;
    MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
    MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
    MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
    MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
    MPU_InitStruct.Number = MPU_REGION_NUMBER2;
    MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
    MPU_InitStruct.SubRegionDisable = 0x00;
    MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;

    HAL_MPU_ConfigRegion(&MPU_InitStruct);

    /*ʹ<><CAB9> MPU */
    HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
}

/**
  * @brief  ʹ<EFBFBD><EFBFBD> L1-Cache
  */
void Cache_Enable(void)
{
    SCB_EnableICache();  //ʹ<><CAB9> I-Cache
    SCB_EnableDCache();  //ʹ<><CAB9> D-Cache
    SCB->CACR |= 1 << 2; //ǿ<><C7BF> D-Cache͸д
}

/**
  * @brief  <EFBFBD><EFBFBD>ʼ<EFBFBD><EFBFBD>ϵͳʱ<EFBFBD><EFBFBD>
  * @param  plln: PLL1 <EFBFBD><EFBFBD>Ƶϵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>PLL<EFBFBD><EFBFBD>Ƶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡֵ<EFBFBD><EFBFBD>Χ<EFBFBD><EFBFBD>4~512
  * @param  pllm: PLL1 Ԥ<EFBFBD><EFBFBD>Ƶϵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>PLL֮ǰ<EFBFBD>ķ<EFBFBD>Ƶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡֵ<EFBFBD><EFBFBD>Χ<EFBFBD><EFBFBD>2~63
  * @param  pllp: PLL1 <EFBFBD><EFBFBD> p <EFBFBD><EFBFBD>Ƶϵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>PLL֮<EFBFBD><EFBFBD><EFBFBD>ķ<EFBFBD>Ƶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊϵͳʱ<EFBFBD>ӣ<EFBFBD>ȡֵ<EFBFBD><EFBFBD>Χ<EFBFBD><EFBFBD>2~128<EFBFBD><EFBFBD><EFBFBD>ұ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 2 <EFBFBD>ı<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
  * @param  pllq: PLL1 <EFBFBD><EFBFBD> q <EFBFBD><EFBFBD>Ƶϵ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>PLL֮<EFBFBD><EFBFBD><EFBFBD>ķ<EFBFBD>Ƶ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>ȡֵ<EFBFBD><EFBFBD>Χ<EFBFBD><EFBFBD>1~128.
  * @retval <EFBFBD>ɹ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 0<EFBFBD><EFBFBD>ʧ<EFBFBD>ܷ<EFBFBD><EFBFBD><EFBFBD> 1
  */
uint8_t Clock_Init(uint32_t plln, uint32_t pllm, uint32_t pllp, uint32_t pllq)
{
    HAL_StatusTypeDef ret = HAL_OK;
    RCC_ClkInitTypeDef RCC_ClkInitStruct;
    RCC_OscInitTypeDef RCC_OscInitStruct;

    MODIFY_REG(PWR->CR3, PWR_CR3_SCUEN, 0);
    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);

    while ((PWR->D3CR & (PWR_D3CR_VOSRDY)) != PWR_D3CR_VOSRDY)
    {
    }

    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
    RCC_OscInitStruct.HSEState = RCC_HSE_ON;
    RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
    RCC_OscInitStruct.CSIState = RCC_CSI_OFF;
    RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
    RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;

    RCC_OscInitStruct.PLL.PLLN = plln;
    RCC_OscInitStruct.PLL.PLLM = pllm;
    RCC_OscInitStruct.PLL.PLLP = pllp;
    RCC_OscInitStruct.PLL.PLLQ = pllq;

    RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
    RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
    ret = HAL_RCC_OscConfig(&RCC_OscInitStruct);
    if (ret != HAL_OK)
        return 1;

    // QSPI_Enable_Memmapmode(); //QSPI<50>ڴ<EFBFBD>ӳ<EFBFBD><D3B3>ģʽ,<2C><>Ҫ<EFBFBD><D2AA>ʱ<EFBFBD>ӳ<EFBFBD>ʼ<EFBFBD><CABC>֮ǰ<D6AE><C7B0><EFBFBD><EFBFBD>,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>и<EFBFBD><D0B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>

    RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK |
                                   RCC_CLOCKTYPE_HCLK |
                                   RCC_CLOCKTYPE_D1PCLK1 |
                                   RCC_CLOCKTYPE_PCLK1 |
                                   RCC_CLOCKTYPE_PCLK2 |
                                   RCC_CLOCKTYPE_D3PCLK1);

    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
    RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
    RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
    RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
    RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
    RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
    RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV4;
    ret = HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
    if (ret != HAL_OK)
        return 1;

    __HAL_RCC_CSI_ENABLE();
    __HAL_RCC_SYSCFG_CLK_ENABLE();
    HAL_EnableCompensationCell();

    return 0;
}

/**
  * @brief  <EFBFBD>ж<EFBFBD> I_Cache <EFBFBD>Ƿ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
  * @retval <EFBFBD>رշ<EFBFBD><EFBFBD><EFBFBD> 0<EFBFBD><EFBFBD><EFBFBD>򿪷<EFBFBD><EFBFBD><EFBFBD> 1
  */
uint8_t Get_ICacheSta(void)
{
    uint8_t sta;
    sta = ((SCB->CCR) >> 17) & 0X01;
    return sta;
}

/**
  * @brief  <EFBFBD>ж<EFBFBD> I_Dache <EFBFBD>Ƿ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
  * @retval <EFBFBD>رշ<EFBFBD><EFBFBD><EFBFBD> 0<EFBFBD><EFBFBD><EFBFBD>򿪷<EFBFBD><EFBFBD><EFBFBD> 1
  */
uint8_t Get_DCacheSta(void)
{
    uint8_t sta;
    sta = ((SCB->CCR) >> 16) & 0X01;
    return sta;
}

/**
  * @brief  QSPI <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڴ<EFBFBD>ӳ<EFBFBD><EFBFBD>ģʽ
  */
void QSPI_Enable_Memmapmode(void)
{
    uint32_t tempreg = 0;
    volatile uint32_t *data_reg = &QUADSPI->DR;
    GPIO_InitTypeDef qspi_gpio;

    RCC->AHB4ENR |= 1 << 1;  //ʹ<><CAB9> PORTB ʱ<><CAB1>
    RCC->AHB4ENR |= 1 << 5;  //ʹ<><CAB9> PORTF ʱ<><CAB1>
    RCC->AHB3ENR |= 1 << 14; //QSPI ʱ<><CAB1>ʹ<EFBFBD><CAB9>

    qspi_gpio.Pin = GPIO_PIN_6; //PB6 AF10
    qspi_gpio.Mode = GPIO_MODE_AF_PP;
    qspi_gpio.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
    qspi_gpio.Pull = GPIO_NOPULL;
    qspi_gpio.Alternate = GPIO_AF10_QUADSPI;
    HAL_GPIO_Init(GPIOB, &qspi_gpio);

    qspi_gpio.Pin = GPIO_PIN_2; //PB2 AF9
    qspi_gpio.Alternate = GPIO_AF9_QUADSPI;
    HAL_GPIO_Init(GPIOB, &qspi_gpio);

    qspi_gpio.Pin = GPIO_PIN_6 | GPIO_PIN_7; //PF6 7 AF9
    qspi_gpio.Alternate = GPIO_AF9_QUADSPI;
    HAL_GPIO_Init(GPIOF, &qspi_gpio);

    qspi_gpio.Pin = GPIO_PIN_8 | GPIO_PIN_9; //PF8 9 AF10
    qspi_gpio.Alternate = GPIO_AF10_QUADSPI;
    HAL_GPIO_Init(GPIOF, &qspi_gpio);

    //QSPI <20><><EFBFBD>ã<EFBFBD><C3A3>ο<EFBFBD> QSPI ʵ<><CAB5><EFBFBD><EFBFBD> QSPI_Init <20><><EFBFBD><EFBFBD>
    RCC->AHB3RSTR |= 1 << 14;    //<2F><>λ QSPI
    RCC->AHB3RSTR &= ~(1 << 14); //ֹͣ<CDA3><D6B9>λ QSPI
    while (QUADSPI->SR & (1 << 5))
        ;                      //<2F>ȴ<EFBFBD> BUSY λ<><CEBB><EFBFBD><EFBFBD>
    QUADSPI->CR = 0X01000310;  //<2F><><EFBFBD><EFBFBD> CR <20>Ĵ<EFBFBD><C4B4><EFBFBD>
    QUADSPI->DCR = 0X00160401; //<2F><><EFBFBD><EFBFBD> DCR <20>Ĵ<EFBFBD><C4B4><EFBFBD>
    QUADSPI->CR |= 1 << 0;     //ʹ<><CAB9> QSPI

    //ע<>⣺QSPI QE λ<><CEBB>ʹ<EFBFBD>ܣ<EFBFBD><DCA3><EFBFBD> QSPI <20><>д<EFBFBD>㷨<EFBFBD><E3B7A8><EFBFBD>棬<EFBFBD><E6A3AC><EFBFBD>Ѿ<EFBFBD><D1BE><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
    //<2F><><EFBFBD>ԣ<EFBFBD><D4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Բ<EFBFBD><D4B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> QE λ<><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD> QE λ<><CEBB> 1 <20>Ĵ<EFBFBD><C4B4><EFBFBD>
    //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ͨ<EFBFBD><CDA8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>أ<EFBFBD>ֱ<EFBFBD><D6B1><EFBFBD><EFBFBD>¼<EFBFBD><C2BC><EFBFBD>ⲿ QSPI FLASH<53><48><EFBFBD>Dz<EFBFBD><C7B2><EFBFBD><EFBFBD>õ<EFBFBD>
    //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֱ<EFBFBD><D6B1><EFBFBD><EFBFBD>¼<EFBFBD><C2BC><EFBFBD>ⲿ QSPI FLASH Ҳ<><D2B2><EFBFBD><EFBFBD><EFBFBD>ã<EFBFBD><C3A3><EFBFBD><EFBFBD><EFBFBD>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> QE λ<><CEBB> 1 <20>Ĵ<EFBFBD><C4B4><EFBFBD>

    //W25QXX <20><><EFBFBD><EFBFBD> QPI ģʽ<C4A3><CABD>0X38ָ<38>
    while (QUADSPI->SR & (1 << 5))
        ;                      //<2F>ȴ<EFBFBD> BUSY λ<><CEBB><EFBFBD><EFBFBD>
    QUADSPI->CCR = 0X00000138; //<2F><><EFBFBD><EFBFBD> 0X38 ָ<>W25QXX <20><><EFBFBD><EFBFBD> QPI ģʽ
    while ((QUADSPI->SR & (1 << 1)) == 0)
        ;                   //<2F>ȴ<EFBFBD>ָ<EFBFBD><EFBFBD><EEB7A2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
    QUADSPI->FCR |= 1 << 1; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɱ<EFBFBD>־λ

    //W25QXX дʹ<D0B4>ܣ<EFBFBD>0X06ָ<36>
    while (QUADSPI->SR & (1 << 5))
        ;                      //<2F>ȴ<EFBFBD> BUSY λ<><CEBB><EFBFBD><EFBFBD>
    QUADSPI->CCR = 0X00000106; //<2F><><EFBFBD><EFBFBD> 0X06 ָ<>W25QXX дʹ<D0B4><CAB9>
    while ((QUADSPI->SR & (1 << 1)) == 0)
        ;                   //<2F>ȴ<EFBFBD>ָ<EFBFBD><EFBFBD><EEB7A2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
    QUADSPI->FCR |= 1 << 1; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɱ<EFBFBD>־λ

    //W25QXX <20><><EFBFBD><EFBFBD> QPI <20><><EFBFBD>ض<EFBFBD><D8B6><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>0XC0<43><30>
    while (QUADSPI->SR & (1 << 5))
        ;                      //<2F>ȴ<EFBFBD> BUSY λ<><CEBB><EFBFBD><EFBFBD>
    QUADSPI->CCR = 0X030003C0; //<2F><><EFBFBD><EFBFBD> 0XC0 ָ<>W25QXX <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
    QUADSPI->DLR = 0;
    while ((QUADSPI->SR & (1 << 2)) == 0)
        ;                                   //<2F>ȴ<EFBFBD> FTF
    *(volatile uint8_t *)data_reg = 3 << 4; //<2F><><EFBFBD><EFBFBD> P4&P5=11<31><31>8 <20><> dummy clocks<6B><73>104M
    QUADSPI->CR |= 1 << 2;                  //<2F><>ֹ<EFBFBD><D6B9><EFBFBD><EFBFBD>
    while ((QUADSPI->SR & (1 << 1)) == 0)
        ;                   //<2F>ȴ<EFBFBD><C8B4><EFBFBD><EFBFBD>ݷ<EFBFBD><DDB7><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
    QUADSPI->FCR |= 1 << 1; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɱ<EFBFBD>־λ
    while (QUADSPI->SR & (1 << 5))
        ; //<2F>ȴ<EFBFBD> BUSY λ<><CEBB><EFBFBD><EFBFBD>

    //MemroyMap ģʽ<C4A3><CABD><EFBFBD><EFBFBD>
    while (QUADSPI->SR & (1 << 5))
        ;                   //<2F>ȴ<EFBFBD> BUSY λ<><CEBB><EFBFBD><EFBFBD>
    QUADSPI->ABR = 0;       //<2F><><EFBFBD><EFBFBD><EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD><EFBFBD><EFBFBD>Ϊ 0<><30>ʵ<EFBFBD><CAB5><EFBFBD>Ͼ<EFBFBD><CFBE><EFBFBD> W25Q 0XEB ָ<><D6B8><EFBFBD><EFBFBD> M0~M7=0
    tempreg = 0XEB;         //INSTRUCTION[7:0]=0XEB<45><42><EFBFBD><EFBFBD><EFBFBD><EFBFBD> 0XEB ָ<>Fast Read QUAD I/O<><4F>
    tempreg |= 3 << 8;      //IMODE[1:0]=3<><33><EFBFBD><EFBFBD><EFBFBD>ߴ<EFBFBD><DFB4><EFBFBD>ָ<EFBFBD><D6B8>
    tempreg |= 3 << 10;     //ADDRESS[1:0]=3<><33><EFBFBD><EFBFBD><EFBFBD>ߴ<EFBFBD><DFB4><EFBFBD><EFBFBD><EFBFBD>ַ
    tempreg |= 2 << 12;     //ADSIZE[1:0]=2<><32>24λ<34><CEBB>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD>
    tempreg |= 3 << 14;     //ABMODE[1:0]=3<><33><EFBFBD><EFBFBD><EFBFBD>ߴ<EFBFBD><DFB4>佻<EFBFBD><E4BDBB><EFBFBD>ֽ<EFBFBD>
    tempreg |= 0 << 16;     //ABSIZE[1:0]=0<><30>8λ<38><CEBB><EFBFBD><EFBFBD><EFBFBD>ֽ<EFBFBD> (M0~M7)
    tempreg |= 6 << 18;     //DCYC[4:0]=6<><36>6<EFBFBD><36>dummy<6D><79><EFBFBD><EFBFBD>
    tempreg |= 3 << 24;     //DMODE[1:0]=3<><33><EFBFBD><EFBFBD><EFBFBD>ߴ<EFBFBD><DFB4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
    tempreg |= 3 << 26;     //FMODE[1:0]=3<><33><EFBFBD>ڴ<EFBFBD>ӳ<EFBFBD><D3B3>ģʽ
    QUADSPI->CCR = tempreg; //<2F><><EFBFBD><EFBFBD>CCR<43>Ĵ<EFBFBD><C4B4><EFBFBD>

    //<2F><><EFBFBD><EFBFBD> QSPI FLASH <20>ռ<EFBFBD><D5BC><EFBFBD>MPU<50><55><EFBFBD><EFBFBD>
    SCB->SHCSR &= ~(1 << 16);        //<2F><>ֹ MemManage
    MPU->CTRL &= ~(1 << 0);          //<2F><>ֹ MPU
    MPU->RNR = 0;                    //<2F><><EFBFBD>ñ<EFBFBD><C3B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ 0 (1~7 <20><><EFBFBD>Ը<EFBFBD><D4B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڴ<EFBFBD><DAB4><EFBFBD>)
    MPU->RBAR = 0X90000000;          //<2F><><EFBFBD><EFBFBD>ַΪ 0X9000 000<30><30><EFBFBD><EFBFBD> QSPI <20><><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>ַ
    MPU->RASR = 0X0303002D;          //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ر<EFBFBD><D8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(<28><>ֹ<EFBFBD><D6B9><EFBFBD>ã<EFBFBD><C3A3><EFBFBD><EFBFBD><EFBFBD> cache<68><65><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>)
    MPU->CTRL = (1 << 2) | (1 << 0); //ʹ<><CAB9> PRIVDEFENA<4E><41>ʹ<EFBFBD><CAB9> MPU
    SCB->SHCSR |= 1 << 16;           //ʹ<><CAB9> MemManage
}

#if defined(__clang__) //ʹ<><CAB9>V6<56><36><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(clang)
//THUMBָ<42>֧<EEB2BB>ֻ<EFBFBD><D6BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>·<EFBFBD><C2B7><EFBFBD>ʵ<EFBFBD><CAB5>ִ<EFBFBD>л<EFBFBD><D0BB><EFBFBD>ָ<EFBFBD><D6B8>WFI
void __attribute__((noinline)) WFI_SET(void)
{
    __asm__("wfi");
}

//<2F>ر<EFBFBD><D8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>(<28><><EFBFBD>Dz<EFBFBD><C7B2><EFBFBD><EFBFBD><EFBFBD>fault<6C><74>NMI<4D>ж<EFBFBD>)
void __attribute__((noinline)) INTX_DISABLE(void)
{
    __asm__("cpsid i \t\n"
            "bx lr");
}

//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
void __attribute__((noinline)) INTX_ENABLE(void)
{
    __asm__("cpsie i \t\n"
            "bx lr");
}

//<2F><><EFBFBD><EFBFBD>ջ<EFBFBD><D5BB><EFBFBD><EFBFBD>ַ
//addr:ջ<><D5BB><EFBFBD><EFBFBD>ַ
void __attribute__((noinline)) MSR_MSP(uint32_t addr)
{
    __asm__("msr msp, r0 \t\n"
            "bx r14");
}
#elif defined(__CC_ARM) //ʹ<><CAB9>V5<56><35><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(ARMCC)

//THUMBָ<42>֧<EEB2BB>ֻ<EFBFBD><D6BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>·<EFBFBD><C2B7><EFBFBD>ʵ<EFBFBD><CAB5>ִ<EFBFBD>л<EFBFBD><D0BB><EFBFBD>ָ<EFBFBD><D6B8>WFI
__asm void WFI_SET(void)
{
    WFI;
}
//<2F>ر<EFBFBD><D8B1><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>(<28><><EFBFBD>Dz<EFBFBD><C7B2><EFBFBD><EFBFBD><EFBFBD>fault<6C><74>NMI<4D>ж<EFBFBD>)
__asm void INTX_DISABLE(void)
{
    CPSID I
        BX LR
}
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
__asm void INTX_ENABLE(void)
{
    CPSIE I
        BX LR
}
//<2F><><EFBFBD><EFBFBD>ջ<EFBFBD><D5BB><EFBFBD><EFBFBD>ַ
//addr:ջ<><D5BB><EFBFBD><EFBFBD>ַ
__asm void MSR_MSP(uint32_t addr)
{
    MSR MSP, r0 //set Main Stack value
                 BX r14
}

#endif