2017-10-28 11:27:06 +02:00
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/**
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* Author Wojciech Domski <Wojciech.Domski@gmail.com>
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* www: www.Domski.pl
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*
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* work based on DORJI.COM sample code and
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* https://github.com/realspinner/SX1278_LoRa
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*/
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#ifndef __SX1278_H__
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#define __SX1278_H__
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#include <stdint.h>
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#include <stdbool.h>
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#define SX1278_MAX_PACKET 256
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#define SX1278_DEFAULT_TIMEOUT 3000
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//RFM98 Internal registers Address
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/********************LoRa mode***************************/
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#define LR_RegFifo 0x00
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// Common settings
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#define LR_RegOpMode 0x01
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#define LR_RegFrMsb 0x06
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#define LR_RegFrMid 0x07
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#define LR_RegFrLsb 0x08
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// Tx settings
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#define LR_RegPaConfig 0x09
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#define LR_RegPaRamp 0x0A
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#define LR_RegOcp 0x0B
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// Rx settings
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#define LR_RegLna 0x0C
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// LoRa registers
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#define LR_RegFifoAddrPtr 0x0D
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#define LR_RegFifoTxBaseAddr 0x0E
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#define LR_RegFifoRxBaseAddr 0x0F
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#define LR_RegFifoRxCurrentaddr 0x10
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#define LR_RegIrqFlagsMask 0x11
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#define LR_RegIrqFlags 0x12
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#define LR_RegRxNbBytes 0x13
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#define LR_RegRxHeaderCntValueMsb 0x14
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#define LR_RegRxHeaderCntValueLsb 0x15
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#define LR_RegRxPacketCntValueMsb 0x16
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#define LR_RegRxPacketCntValueLsb 0x17
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#define LR_RegModemStat 0x18
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#define LR_RegPktSnrValue 0x19
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#define LR_RegPktRssiValue 0x1A
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#define LR_RegRssiValue 0x1B
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#define LR_RegHopChannel 0x1C
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#define LR_RegModemConfig1 0x1D
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#define LR_RegModemConfig2 0x1E
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#define LR_RegSymbTimeoutLsb 0x1F
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#define LR_RegPreambleMsb 0x20
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#define LR_RegPreambleLsb 0x21
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#define LR_RegPayloadLength 0x22
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#define LR_RegMaxPayloadLength 0x23
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#define LR_RegHopPeriod 0x24
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#define LR_RegFifoRxByteAddr 0x25
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2020-08-26 11:05:42 +02:00
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#define LR_RegModemConfig3 0x26
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// I/O settings
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#define REG_LR_DIOMAPPING1 0x40
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#define REG_LR_DIOMAPPING2 0x41
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// Version
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#define REG_LR_VERSION 0x42
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// Additional settings
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#define REG_LR_PLLHOP 0x44
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#define REG_LR_TCXO 0x4B
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#define REG_LR_PADAC 0x4D
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#define REG_LR_FORMERTEMP 0x5B
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#define REG_LR_AGCREF 0x61
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#define REG_LR_AGCTHRESH1 0x62
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#define REG_LR_AGCTHRESH2 0x63
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#define REG_LR_AGCTHRESH3 0x64
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/********************FSK/ook mode***************************/
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#define RegFIFO 0x00
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#define RegOpMode 0x01
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#define RegBitRateMsb 0x02
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#define RegBitRateLsb 0x03
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#define RegFdevMsb 0x04
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#define RegFdevLsb 0x05
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#define RegFreqMsb 0x06
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#define RegFreqMid 0x07
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#define RegFreqLsb 0x08
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#define RegPaConfig 0x09
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#define RegPaRamp 0x0a
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#define RegOcp 0x0b
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#define RegLna 0x0c
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#define RegRxConfig 0x0d
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#define RegRssiConfig 0x0e
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#define RegRssiCollision 0x0f
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#define RegRssiThresh 0x10
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#define RegRssiValue 0x11
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#define RegRxBw 0x12
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#define RegAfcBw 0x13
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#define RegOokPeak 0x14
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#define RegOokFix 0x15
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#define RegOokAvg 0x16
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#define RegAfcFei 0x1a
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#define RegAfcMsb 0x1b
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#define RegAfcLsb 0x1c
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#define RegFeiMsb 0x1d
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#define RegFeiLsb 0x1e
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#define RegPreambleDetect 0x1f
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#define RegRxTimeout1 0x20
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#define RegRxTimeout2 0x21
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#define RegRxTimeout3 0x22
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#define RegRxDelay 0x23
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#define RegOsc 0x24
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#define RegPreambleMsb 0x25
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#define RegPreambleLsb 0x26
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#define RegSyncConfig 0x27
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#define RegSyncValue1 0x28
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#define RegSyncValue2 0x29
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#define RegSyncValue3 0x2a
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#define RegSyncValue4 0x2b
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#define RegSyncValue5 0x2c
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#define RegSyncValue6 0x2d
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#define RegSyncValue7 0x2e
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#define RegSyncValue8 0x2f
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#define RegPacketConfig1 0x30
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#define RegPacketConfig2 0x31
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#define RegPayloadLength 0x32
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#define RegNodeAdrs 0x33
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#define RegBroadcastAdrs 0x34
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#define RegFifoThresh 0x35
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#define RegSeqConfig1 0x36
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#define RegSeqConfig2 0x37
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#define RegTimerResol 0x38
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#define RegTimer1Coef 0x39
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2020-08-26 11:05:42 +02:00
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#define RegSyncWord 0x39
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2017-10-28 11:27:06 +02:00
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#define RegTimer2Coef 0x3a
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#define RegImageCal 0x3b
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#define RegTemp 0x3c
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#define RegLowBat 0x3d
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#define RegIrqFlags1 0x3e
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#define RegIrqFlags2 0x3f
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#define RegDioMapping1 0x40
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#define RegDioMapping2 0x41
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#define RegVersion 0x42
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#define RegPllHop 0x44
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#define RegPaDac 0x4d
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#define RegBitRateFrac 0x5d
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/**********************************************************
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**Parameter table define
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**********************************************************/
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#define SX1278_POWER_20DBM 0
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#define SX1278_POWER_17DBM 1
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#define SX1278_POWER_14DBM 2
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#define SX1278_POWER_11DBM 3
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static const uint8_t SX1278_Power[4] = { 0xFF, //20dbm
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0xFC, //17dbm
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0xF9, //14dbm
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0xF6, //11dbm
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};
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#define SX1278_LORA_SF_6 0
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#define SX1278_LORA_SF_7 1
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#define SX1278_LORA_SF_8 2
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#define SX1278_LORA_SF_9 3
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#define SX1278_LORA_SF_10 4
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#define SX1278_LORA_SF_11 5
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#define SX1278_LORA_SF_12 6
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static const uint8_t SX1278_SpreadFactor[7] = { 6, 7, 8, 9, 10, 11, 12 };
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#define SX1278_LORA_BW_7_8KHZ 0
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#define SX1278_LORA_BW_10_4KHZ 1
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#define SX1278_LORA_BW_15_6KHZ 2
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#define SX1278_LORA_BW_20_8KHZ 3
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#define SX1278_LORA_BW_31_2KHZ 4
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#define SX1278_LORA_BW_41_7KHZ 5
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#define SX1278_LORA_BW_62_5KHZ 6
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#define SX1278_LORA_BW_125KHZ 7
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#define SX1278_LORA_BW_250KHZ 8
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#define SX1278_LORA_BW_500KHZ 9
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static const uint8_t SX1278_LoRaBandwidth[10] = { 0, // 7.8KHz,
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1, // 10.4KHz,
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2, // 15.6KHz,
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3, // 20.8KHz,
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4, // 31.2KHz,
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5, // 41.7KHz,
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6, // 62.5KHz,
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7, // 125.0KHz,
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8, // 250.0KHz,
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9 // 500.0KHz
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};
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2020-08-26 11:05:42 +02:00
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//Coding rate
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#define SX1278_LORA_CR_4_5 0
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#define SX1278_LORA_CR_4_6 1
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#define SX1278_LORA_CR_4_7 2
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#define SX1278_LORA_CR_4_8 3
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static const uint8_t SX1278_CodingRate[4] = { 0x01, 0x02, 0x03, 0x04};
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//CRC Enable
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#define SX1278_LORA_CRC_EN 0
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#define SX1278_LORA_CRC_DIS 1
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static const uint8_t SX1278_CRC_Sum[2] = { 0x01, 0x00};
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2017-10-28 11:27:06 +02:00
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typedef enum _SX1278_STATUS {
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SLEEP, STANDBY, TX, RX
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} SX1278_Status_t;
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typedef struct {
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int pin;
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void * port;
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} SX1278_hw_dio_t;
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typedef struct {
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SX1278_hw_dio_t reset;
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SX1278_hw_dio_t dio0;
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SX1278_hw_dio_t nss;
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void * spi;
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} SX1278_hw_t;
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typedef struct {
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SX1278_hw_t * hw;
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2020-08-26 11:05:42 +02:00
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uint64_t frequency;
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2017-10-28 11:27:06 +02:00
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uint8_t power;
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uint8_t LoRa_Rate;
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uint8_t LoRa_BW;
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2020-08-26 11:05:42 +02:00
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uint8_t LoRa_CR;
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uint8_t LoRa_CRC_sum;
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2017-10-28 11:27:06 +02:00
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uint8_t packetLength;
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SX1278_Status_t status;
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uint8_t rxBuffer[SX1278_MAX_PACKET];
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uint8_t readBytes;
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} SX1278_t;
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//hardware
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2020-08-26 11:05:42 +02:00
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void SX1278_hw_init(SX1278_hw_t * hw);
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void SX1278_hw_SetNSS(SX1278_hw_t * hw, int value);
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void SX1278_hw_Reset(SX1278_hw_t * hw);
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void SX1278_hw_SPICommand(SX1278_hw_t * hw, uint8_t cmd);
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uint8_t SX1278_hw_SPIReadByte(SX1278_hw_t * hw);
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void SX1278_hw_DelayMs(uint32_t msec);
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int SX1278_hw_GetDIO0(SX1278_hw_t * hw);
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2017-10-28 11:27:06 +02:00
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//logic
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uint8_t SX1278_SPIRead(SX1278_t * module, uint8_t addr);
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void SX1278_SPIWrite(SX1278_t * module, uint8_t addr, uint8_t cmd);
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2020-08-26 11:05:42 +02:00
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void SX1278_SPIBurstRead(SX1278_t * module, uint8_t addr, uint8_t * rxBuf,
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uint8_t length);
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2020-08-26 11:05:42 +02:00
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void SX1278_SPIBurstWrite(SX1278_t * module, uint8_t addr, uint8_t * txBuf,
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uint8_t length);
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void SX1278_DIO0_InterruptHandler(SX1278_t * module);
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2020-08-26 11:05:42 +02:00
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void SX1278_config(SX1278_t * module);
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2017-10-28 11:27:06 +02:00
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void SX1278_entryLoRa(SX1278_t * module);
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void SX1278_clearLoRaIrq(SX1278_t * module);
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int SX1278_LoRaEntryRx(SX1278_t * module, uint8_t length, uint32_t timeout);
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uint8_t SX1278_LoRaRxPacket(SX1278_t * module);
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int SX1278_LoRaEntryTx(SX1278_t * module, uint8_t length, uint32_t timeout);
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int SX1278_LoRaTxPacket(SX1278_t * module, uint8_t * txBuf, uint8_t length,
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2017-10-28 11:27:06 +02:00
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uint32_t timeout);
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2020-08-26 11:05:42 +02:00
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void SX1278_init(SX1278_t * module, uint64_t frequency, uint8_t power,
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uint8_t LoRa_Rate, uint8_t LoRa_BW, uint8_t LoRa_CR, uint8_t LoRa_CRC_sum, uint8_t packetLength);
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2017-10-28 11:27:06 +02:00
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2020-08-26 11:05:42 +02:00
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int SX1278_transmit(SX1278_t * module, uint8_t * txBuf, uint8_t length,
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uint32_t timeout);
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int SX1278_(SX1278_t * module, uint8_t length, uint32_t timeoutT);
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uint8_t SX1278_available(SX1278_t * module);
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uint8_t SX1278_read(SX1278_t * module, uint8_t * rxBuf, uint8_t length);
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2017-10-28 11:27:06 +02:00
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uint8_t SX1278_RSSI_LoRa(SX1278_t * module);
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uint8_t SX1278_RSSI(SX1278_t * module);
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void SX1278_standby(SX1278_t * module);
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void SX1278_sleep(SX1278_t * module);
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#endif
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